Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes cost-effective products by using wafer-level packaging instead chip-level process. However, TSV leakage has become critical concern in BEOL In this paper, Cu-fulfilled via-middle with 100 µm depth embedded 0.18 CMOS process sensor application is presented, focusing on analysis optimization leakage. By etch process, substrate defect, thermal processing co-optimization, failure can be successfully avoided, very instructive improvement yield as well device performance advanced semiconductor technology.